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High-speed ADCs (≥10 MSPS)

ADS54J60

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Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS54J60

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1000 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 70.9 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1000 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 70.9 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 16-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –159 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (including interleaving tones)
    • SFDR: 89 dBc (except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)
  • 16-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –159 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (including interleaving tones)
    • SFDR: 89 dBc (except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
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Type Title Date
* Data sheet ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. D) PDF | HTML 17 Apr 2019
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Implementing the External DC Offset Correction Block in the ADS54J60 (Rev. A) PDF | HTML 13 Jun 2023
User guide HSDC Pro with Xilinx KCU105 01 Mar 2017
Technical article How to minimize filter loss when you drive an ADC PDF | HTML 20 Oct 2016
Analog Design Journal JESD204B over optical fiber enables new architecture for phased-array radar 26 Jan 2016
EVM User's guide ADS54J60EVM User's Guide (Rev. A) 11 Jan 2016
Technical article RF sampling: interleaving builds faster ADCs PDF | HTML 29 Oct 2015
EVM User's guide TSW54J60 Evaluation Module User's Guide (Rev. A) 21 Sep 2015
Technical article RF sampling: How over-sampling is cheating physics PDF | HTML 21 Aug 2015

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