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Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADS5560

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16-Bit, 40-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS5560

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 40 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 250 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 3.6 Power consumption (typ) (mW) 674 Architecture Pipeline SNR (dB) 84.3 ENOB (bit) 13.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 40 Resolution (Bits) 16 Number of input channels 1 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 250 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 3.6 Power consumption (typ) (mW) 674 Architecture Pipeline SNR (dB) 84.3 ENOB (bit) 13.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • 16-Bit Resolution
  • Maximum Sample Rate:
    • ADS5562: 80 MSPS
    • ADS5560: 40 MSPS
  • Total Power:
    • 865 mW at 80 MSPS
    • 674 mW at 40 MSPS
  • No Missing Codes
  • High SNR: 84 dBFS (3 MHz IF)
  • SFDR: 85 dBc (3 MHz IF)
  • Low-Frequency Noise Suppression Mode
  • Programmable Fine Gain, 1-dB steps Until
    6-dB Maximum Gain
  • Double Data-Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Internal and External Reference Support
  • 3.3-V Analog and Digital Supply
  • Pin-for-Pin With ADS5547 Family
  • 48-VQFN Package (7.00 mm × 7.00 mm)
  • 16-Bit Resolution
  • Maximum Sample Rate:
    • ADS5562: 80 MSPS
    • ADS5560: 40 MSPS
  • Total Power:
    • 865 mW at 80 MSPS
    • 674 mW at 40 MSPS
  • No Missing Codes
  • High SNR: 84 dBFS (3 MHz IF)
  • SFDR: 85 dBc (3 MHz IF)
  • Low-Frequency Noise Suppression Mode
  • Programmable Fine Gain, 1-dB steps Until
    6-dB Maximum Gain
  • Double Data-Rate (DDR) LVDS and Parallel
    CMOS Output Options
  • Internal and External Reference Support
  • 3.3-V Analog and Digital Supply
  • Pin-for-Pin With ADS5547 Family
  • 48-VQFN Package (7.00 mm × 7.00 mm)

The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz.

In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain.

Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package.

The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates.

The device is specified over the industrial temperature range of –40°C to 85°C.

The ADS556x is a high-performance 16-bit family of ADCs with sampling rates up to 80 MSPS. The device supports very-high SNR for input frequencies in the first Nyquist zone. The device includes a low-frequency noise suppression mode that improves the noise from DC to about 1 MHz.

In addition to high performance, the device offers several flexible features such as output interface (either Double Data Rate [DDR] LVDS or parallel CMOS) and fine gain in 1-dB steps until 6-dB maximum gain.

Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling capacitors, have been used to achieve significant savings in pin count. This innovation results in a compact 7-mm × 7-mm 48-pin VQFN package.

The device can be put in an external reference mode, where the VCM pin behaves as the external reference input. For applications where power is important, the ADS556x device offers power down modes and automatic power scaling at lower sample rates.

The device is specified over the industrial temperature range of –40°C to 85°C.
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Technical documentation

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Type Title Date
* Data sheet ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs datasheet (Rev. B) PDF | HTML 13 Jan 2016
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
More literature TI and Altera Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
More literature TI and Xilinx Ease Design Process with Compatible Evaluation Tools 25 Apr 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
EVM User's guide ADS61x9/55xxEVM User's Guide (Rev B of the EVM board) (Rev. A) 11 Jun 2009
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
EVM User's guide ADS5560/62EVM 04 Dec 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

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